The more difficult the semiconductor process technology is to develop, it is not easy to make more advanced process. In addition to the process miniaturization, 3D stacking technology is another option to continuously improve the performance of semiconductor chips. The foreign media tomshardware reported that researchers at the Institute of Microelectronics (IME) said they had reached technological breakthroughs to improve the performance of semiconductor chips through up to four semiconductor layer stacks. Compared with traditional 2D manufacturing technology, this technology can not only save 50% cost, but also be used in future and platform integration design, such as CPU and GPU, even memory integration, to realize the development of new generation 3D chip stacking.

The new generation of IME semiconductor stacking method combines TSV (silicon through hole technology) after bonding and stacking by face-to-face and back-to-back wafer. The first layer faces the second layer and the second layer faces the first layer. The back of the second semiconductor layer is toward the back of the third layer, and the third layer faces the fourth layer. After the semiconductor layer is combined, IME etchs "compression" through a specially designed path, and finally flows current data through TSV integration.

Compared with SRAM stack technology of TSMC and AMD, IME new technology is further developed. Because amd displays the prototype design of ryzen9 5900x processor with 3D stacking technology, the products with the stacking technology of Taiwan product are only two layers of semiconductor layer, the first layer is CCX of Zen 3 architecture and the second layer is 96MB SRAM temporary storage. The new generation of stack technology, shown by ime researchers, successfully adheres to four independent semiconductor layers through TSV and allows for different technologies to communicate.

The report stressed that the benefits of technology are obvious, that is, to allow chips to be made from wafer of different processes. Intel recently also mentioned the benefits of 3D stack technology, and said that new chip design will develop in the future. However, stack will bring other problems, that is, although 3D stack technology improves chip efficiency, multi-layer stack must also face the difficult heat dissipation problem. In view of the future 3D stack chip heat dissipation demand, there are also many heat dissipation technologies developed, and the future performance is expected.